(1) Field of the Invention
The invention relates to a method of etching metal lines, and more particularly, to a method of etching metal lines with reduced microloading in the manufacture of integrated circuits.
(2) Description of the Prior Art
In the formation of metal lines, a barrier metal layer is deposited over an oxide layer followed by a metal layer, such as aluminum. The aluminum layer is etched where it is not covered by a mask. Next, the barrier layer is etched, and finally an oxide etch or overetch is performed. In the current practice, the problem of microloading is severe. That is, narrow spaces are etched to a smaller depth than are wider spaces. In deep sub-micron technology, where the design rule shrinks the line spacing, the microloading effect is further-aggravated. Microloading can cause problems including severe resist loss, poor wafer planarization, and, in extreme cases, metal shorts at narrow gap regions.
Workers in the art have sought to avoid or reduce the problems of microloading. U.S. Pat. No. 5,582,679 to Lianjun et al teaches higher temperature etching to reduce microloading effects and teaches the use of N2 to form a protective polymer during etching. U.S. Pat. No. 5,556,501 to Collins et al teaches a method of etching with selectivity. U.S. Pat. No. 5,545,289 to Chen et al teaches removing etchant byproducts using a multi-step passivation and stripping process.
A principal object of the present invention is to provide an effective and very manufacturable method of etching metal lines.
Another object of the present invention is to provide a method of etching metal lines with reduced microloading effect.
A further object of the present invention is to provide a method of etching metal lines with reduced microloading effect by introducing a selective etch step.
In accordance with the objects of this invention a new method of etching metal lines with reduced microloading effect is achieved. Semiconductor device structures are provided in and on a semiconductor substrate. The semiconductor device structures are covered with an insulating layer. A barrier metal layer is deposited overlying the insulating layer and a metal layer is deposited overlying the barrier metal layer. The metal layer is covered with a layer of photoresist. The photoresist layer is exposed to actinic light and developed and patterned to form the desired photoresist mask wherein there are both wide spaces and narrow spaces between portions of the photoresist mask. The metal layer is etched away where it is not covered by the photoresist mask wherein the barrier metal layer is reached within the wide spaces while some of the metal layer remains within the narrow spaces. The metal layer remaining within the narrow spaces is selectively etched away. Thereafter, the barrier metal layer not covered by the photoresist mask is etched away wherein the insulating layer is reached within the wide spaces while some of the barrier metal layer remains within the narrow spaces. The barrier metal layer remaining within the narrow spaces is selectively etched away. Thereafter, the insulating layer not covered by the photoresist mask is overetched to complete the metal lines without microloading to in the fabrication of an integrated circuit.